For implementing functions within a semiconductor circuit, it is customary to use a multitude of standard cells in what is called an Application Specific Integrated Circuit (ASIC). This approach has the advantage of providing a compact solution, together with a fast speed of execution of the instructions. However, the realization of an ASIC requires a high level of investments, since an entire set of lithographic masks has to be developed. Additionally, once finalized, the ASIC morphology and functionality cannot be changed.
As an alternative and more flexible solution, Field-Programmable Gate Array (FPGA) circuits are used. In an FPGA cell, a plurality of registers is provided as well as logic resources. By appropriately setting the registers and the logic, any Boolean or sequential function can be implemented between any two or more inputs of the FPGA cell.
In particular, an FPGA cell usually contains one or more look-up tables for realizing the programmable logic functionality.
FIG. 9 illustrates such an exemplary look-up table 9000.
Look-up table 9000 receives two input signals A and B. The look-up table further comprises a plurality of registers 9101-9104. Depending on the logic values assigned to the registers, the look-up table 9000 will realize any Boolean function of the two input signals A and B.
In order to do so, look-up table 9000 comprises a plurality of pass gates 9201-9206 connected between the plurality of registers 9101-9104 and an output node OUT. The plurality of pass gates 9201-9206 are controlled by the input signals A and B and their respective negated versions Ā and B. The negation of the input signal A and B is obtained by means of inverters 9301 and 9302, respectively, connected to input signal A and input signal B.
As a result of such construction, any Boolean function of the input signals A and B can be obtained, depending on the values assigned to registers 9101-9104.
For instance, assuming that the pass gates 9201-9206 are each realized by a single NMOS transistor, as illustrated, when the registers 9101-9104 are, respectively, set to the values 0, 1, 1 and 1, the function realized on the output node OUT by input signals A and B corresponds to an OR function. As an example, if input signal A is set at 1 while input signal B is set at 0, pass gates 9201, 9204 and 9206 will be conducting, while pass gates 9202, 9205 and 9203 will be open. In turn, this implies that the output of register 9103 will be connected to node 9402, which will be itself connected to the output node OUT. Accordingly, the output node OUT will be set at 1, corresponding to the result of the OR function of the input signal A and B being respectively set at 1 and 0.
In the following, a potential physical realization of a look-up table will be described with reference to FIGS. 10A and 10B.
FIG. 10A illustrates a possible layout 10000 of a look-up table. FIG. 10B illustrates an enlarged portion of FIG. 10A.
In FIG. 9, for ease of representation, each of the pass gates 9201-9206 has been realized by a single NMOS transistor. However, in practice, a complementary CMOS couple of NMOS and PMOS transistors are generally used for each pass gate. Accordingly, the layout 10000 of FIG. 10A illustrates the case in which each pass gate is realized by a CMOS couple of transistors. It will be appreciated by those skilled in the art that the functionality carried out by the look-up table of FIG. 9 and the look-up table of FIG. 10A is substantially equivalent.
In particular, as can be seen in FIG. 10A, layout 10000 comprises three regions 10100-10300. The three regions 10100-10300 are substantially similar to each other in that each of them comprises two NMOS transistors 10130, 10140, and two PMOS transistors 10110, 10120. Further, each of regions 10100-10300 operates based on two inputs signals A and B and their negated versions Ā and B, two register signals and one output.
As can be seen in FIG. 10B, region 10100 comprises two PMOS transistors 10110 and 10120, and two NMOS transistors 10130 and 10140. Transistors 10110 and 10130 correspond to a CMOS implementation of pass gate 9201, while transistors 10120 and 10140 correspond to a CMOS implementation of pass gate 9202.
Black squares, such as square 10112, indicate connections to the drain or source of the transistors. The gates of transistors 10110-10140 are, respectively, gates 10111-10141. In the case of region 10100, the four gates 10111-10141 are respectively connected to input signals Ā, A, A and Ā. The gate connections for remaining regions 10200 and 10300 are indicated in FIG. 10A.
Connection lines 10150, 10160 and 10170 are provided in order to connect the drain/sources of the transistors 10110-10140 to either one of the register signals issued by registers 9101-9104 (not illustrated in FIGS. 10A and 10B), and/or to internal nodes of the look-up table, such as nodes 9401 and 9402 and/or to output node OUT.
In the case of region 10100, connection line 10150 connects register 9101 to transistors 10110 and 10130, acting as pass gate 9201, while connection line 10160 connects register 9102 to transistors 10120 and 10140, acting as pass gate 9202. At the same time, connection line 10170 connects the transistors 10110-10140 to internal look-up table node 9401.
A corresponding arrangement is provided for region 10200, realizing pass gates 9204 and 9205 of FIG. 9, and for region 10300, realizing pass gates 9203 and 9206 of FIG. 9.
The schematic of look-up table 9000 and its physical realization via the layout of FIG. 10A can be improved.
In particular, the output node OUT is directly connected to the registers 9101-9104 via the plurality of pass gates 9201-9206. Accordingly, it is necessary for the registers 9101-9104 to have a current drive capability high enough to drive the load on output node OUT. In turn, this implies that such a structure cannot be realized with small registers since they would lack the appropriate current driving capabilities. In particular, small SRAM, small DRAM and registers realized using flash technology are generally not powerful enough for such constructions.
Moreover, the signal from each of the registers 9101-9104 to the output node OUT has to cross several pass gates among pass gates 9201-9206. This increases the propagation delay and, therefore, the operating frequency of the circuit.
Furthermore, each passage through a pass gate 9201-9206 reduces the strength of the signal. For instance, in the case of NMOS or PMOS pass gates, the voltage is reduced. More generally, the strength of the signal is reduced due to the parasitic “ON” resistance of the pass gate. This translates in delay to establish the signal and/or sensitivity to the noise. It is, therefore, customary to insert repeaters inbetween the pass gates 9201-9206. However, this further increases the delay, thereby further slowing down the operating frequency of the circuit.
Additionally, the arrangement of the regions 10100-10300 in a triangular layout, as illustrated in FIG. 10A, makes it difficult to achieve a compact and dense layout, when a plurality of look-up tables 9000 is to be integrated in a single circuit. This has effects on the costs of the FPGA, as well as the reliability, since an irregular layout provides more difficulty for manufacturing.
While this could be solved by placing the three regions in a straight line, this solution is not ideal as the resulting structure loses symmetry and speed, since one region among regions 10100 and 10200 would be placed farther away from region 10300 than the other.